In a large scale integration circuit (LSI), as the degree of integration and the capacity are increased, the circuit size required for a semiconductor device has been gradually decreasing.
In the manufacture of the semiconductor device, a pattern is exposed and transferred onto a resist film formed on a wafer by a reduced projection exposure apparatus generally called a stepper or scanner to form a circuit pattern, using a mask or reticle (hereinafter collectively referred to as mask) having an original image pattern, whereby the semiconductor device is manufactured.
Enhancement of yield is essential, as the manufacture of LSI involves a large manufacturing cost. Meanwhile, recent typical logic devices are under such a condition that the formation of a pattern with a line width of several ten nm is required. In these circumstances, shape defects of a pattern of a mask constitute a major cause of reduction in the yield. More specifically, the shape defect of the mask pattern includes, for example, unevenness (roughness) of the pattern edge (edge roughness), a line width abnormality in the pattern, and a gap abnormality between a target pattern and a pattern adjacent thereto due to pattern positional deviation.
Along with miniaturization of an LSI pattern dimension formed on a semiconductor wafer, the size of the shape defect of the mask pattern is also miniaturized. The dimensional accuracy of the mask is enhanced, whereby the deviation of the process terms and conditions is to be absorbed, and thus, in the inspection of the mask, an extremely small pattern defect is required to be detected. As a result, high inspection accuracy is required of an apparatus, which inspects a pattern of a mask used for transfer in the manufacture of LSI. Japanese patent 4236825 discloses an inspection apparatus for detecting a fine defect on a mask.
Recently, as a technique for forming a fine pattern, nanoimprint lithography (NIL) has attracted attention. In this technique, a template having a nanoscale microstructure is pressured on a specific resist formed on a wafer to form the fine circuit pattern on the resist.
In the nanoimprint technology, to increase productivity, a plurality of duplicate patterns (hereinafter daughter patterns) are produced using a master pattern as an original plate, and the daughter patterns are used in different nanoimprint apparatuses during forming the fine circuit pattern on the resist. The daughter pattern is required to be produced accurately corresponding to the master template. Thus, high inspection accuracy is required for not only the master pattern but also the daughter pattern.
The size of a pattern of photo-mask is generally four times larger than the size of a circuit pattern formed over the wafer. The pattern is reduced and exposed onto a resist on the wafer by a reduced projection exposure device, using the photo-mask, and thereafter, the circuit pattern is developed. Meanwhile, the master pattern and the daughter pattern in nanoimprint lithography are formed to have the same size as the circuit patterns formed on the wafer. Thus, a shape defect in these patterns causes a higher degree of influence to a pattern to be transferred onto the wafer than a shape defect in a pattern of the photo-mask. Accordingly, the detection of pattern defects of the master pattern and daughter pattern requires detection with higher accuracy than the detection of the pattern defect of the photo-mask.
As described above, an inspection apparatus, which detects defects of a master pattern and a daughter pattern, is required. However, these days, when a circuit pattern is being miniaturized, the pattern size is becoming more minute than the resolution of an optical unit in a pattern inspection apparatus. For example, depending on numerical aperture (NA) of an objective lens, in the case of a line width of a pattern formed on a master pattern and daughter pattern is smaller than about 50-60 nm, the pattern cannot be resolved by a light source using DUV (Deep Ultraviolet radiation) light. Thus, although a EB (Electron Beam) source is used, throughput is low, and a problem arises in that the source cannot be mass-produced.
Meanwhile, if the inspection apparatus has the functional capability of managing detected defect information in addition to the inspection function, the yield in the production of a semiconductor wafer can be enhanced. However, in conventional inspection apparatuses, in order to inspect a pattern transferred onto a wafer for a defect after wafer transfer, only a class value based on the number, the size, the position, and the shape of the defect has been monitored and checked (see Japanese patent publication 2004-327465). On the other hand, the defects in the master pattern and the daughter pattern are not monitored and checked, and since whether or not a defect on a wafer is derived from these defects cannot be discriminated, there is a problem that the detected defect information cannot be fed back to a process of producing the master pattern and the daughter pattern.
The present invention has been made in consideration of the above points. Namely, the present invention provides an inspection apparatus and an inspection apparatus system which can inspect a sample having a repeated pattern smaller than a resolution of an optical system, such as a master pattern and a daughter pattern, and manage information obtained from the inspection, resulting in reduction of a failure of a semiconductor device.
Other challenges and advantages of the present invention are apparent from the following description.